module serial_port_input(
		clk,
		rst_n,
		rs232_rx,
		band_set,
		
		data_byte,
		rx_done

);
	input clk			;
	input rst_n			;
	input rs232_rx		;//数据输入
	input [2:0]band_set		;//波特率设置
		
	output data_byte	;//并行数据输出
	output rx_done		;//接收结束信号
	
	//同步寄存，消除亚稳态
	reg s0_rs232_rx,s1_rs232_rx;
	always@(posedge clk or negedge rst_n)
		if(!rst_n) begin
			s0_rs232_rx<=0;
			s1_rs232_rx<=0;
			end
		else begin
				s0_rs232_rx<=rs232_rx;
				s1_rs232_rx<=s0_rs232_rx;
		end

	//数据寄存器
	reg tmp0_rs232_rx,tmp1_rs232_rx;
	always@(posedge clk or negedge rst_n)
		if(!rst_n) begin
			tmp0_rs232_rx<=0;
			tmp1_rs232_rx<=0;
			end
		else begin
				tmp0_rs232_rx<=s1_rs232_rx;
				tmp1_rs232_rx<=tmp0_rs232_rx;
		end
	
	//数据接收下降沿检测
	wire nedege;
	assign nedege=!tmp0_rs232_rx && tmp1_rs232_rx;
	
	
	//不同波特率检测16次所需要的计数
	reg [15:0]bps_dr;
	always@(posedge clk or negedge rst_n)
		if(!rst_n)
			bps_dr<=16'd324;
		else begin
			case(band_set)
				0:bps_dr<=16'd324;
				1:bps_dr<=16'd162;
				2:bps_dr<=16'd80;
				3:bps_dr<=16'd53;
				4:bps_dr<=16'd26;
				default:bps_dr<=16'd324;
			endcase
		end
	
	
		//使能设置
	reg uart_state;
	always@(posedge clk or negedge rst_n)
		if(!rst_n)
			uart_state<=0;
		else if(bps_cnt==8'd159)
					uart_state<=0;
				else if(nedege)
							uart_state<=1'b1;
						else 
							uart_state<=uart_state;
	
	
	//每个波特位的计数
	reg [15:0]div_cnt;
	always@(posedge clk or negedge rst_n)
		if(!rst_n)
			div_cnt<=0;
		else if(uart_state)
					if(div_cnt==bps_dr)
						div_cnt<=0;
					else 
						div_cnt<=div_cnt+1'b1;
				else 
					div_cnt<=0;
					
					
	//采样时钟设置
	reg bps_clk;
	always@(posedge clk or negedge rst_n)
		if(!rst_n)
			bps_clk<=0;
		else if(div_cnt==1'b1)
					bps_clk<=1'b1;
				else 
					bps_clk<=0;
	
	
	//采样时钟计数设置
	reg [7:0]bps_cnt;
	always@(posedge clk or negedge rst_n)
		if(!rst_n)
			bps_cnt<=0;
		else if(bps_cnt==8'd159 || (bps_cnt==8'd12 && (start_bit>2)))
					bps_cnt<=0;
				else if(bps_clk)
							bps_cnt<=bps_cnt+1'b1;
						else 
							bps_cnt<=bps_cnt;
		
		
		
	//信号接收结束设置
	reg rx_done;
	always@(posedge clk or negedge rst_n)
		if(!rst_n)
			rx_done<=0;
		else if(bps_cnt==8'd159)
					rx_done<=1'b1;
				else 
					rx_done<=0;
					
					
				
				
	//rx_done信号处理
	reg [2:0]start_bit;
	reg [2:0]stop_bit;
	reg [2:0] r_data_byte[7:0];
	always@(posedge clk or negedge rst_n)
		if(!rst_n) begin
			start_bit<=3'd0;
			r_data_byte[0]<=3'd0;
			r_data_byte[1]<=3'd0;
			r_data_byte[2]<=3'd0;
			r_data_byte[3]<=3'd0;
			r_data_byte[4]<=3'd0;
			r_data_byte[5]<=3'd0;
			r_data_byte[6]<=3'd0;
			r_data_byte[7]<=3'd0;
			stop_bit<=3'd0;
		end
		else if(bps_clk) begin
					case(bps_cnt)
					0:begin
						start_bit<=3'd0;
						r_data_byte[0]<=3'd0;
						r_data_byte[1]<=3'd0;
						r_data_byte[2]<=3'd0;
						r_data_byte[3]<=3'd0;
						r_data_byte[4]<=3'd0;
						r_data_byte[5]<=3'd0;
						r_data_byte[6]<=3'd0;
						r_data_byte[7]<=3'd0;
						stop_bit<=0;
						end
						
					6,7,8,9,10,11:	start_bit<=start_bit+s1_rs232_rx;
					22,23,24,25,26,27:r_data_byte[0]<=r_data_byte[0]+s1_rs232_rx;	
					38,39,40,41,42,43:r_data_byte[1]<=r_data_byte[1]+s1_rs232_rx;	
					54,55,56,57,58,59:r_data_byte[2]<=r_data_byte[2]+s1_rs232_rx;	
					70,71,72,73,74,75:r_data_byte[3]<=r_data_byte[3]+s1_rs232_rx;	
					86,87,88,89,90,91:r_data_byte[4]<=r_data_byte[4]+s1_rs232_rx;	
					102,103,104,105,106,107:r_data_byte[5]<=r_data_byte[5]+s1_rs232_rx;		
					118,119,120,121,122,123:r_data_byte[6]<=r_data_byte[6]+s1_rs232_rx;		
					134,135,136,137,138,139:r_data_byte[7]<=r_data_byte[7]+s1_rs232_rx;	
					150,151,152,153,154,155:stop_bit<=stop_bit+s1_rs232_rx;	
					
					default: begin
						start_bit<=3'd0;
						r_data_byte[0]<=r_data_byte[0];
						r_data_byte[1]<=r_data_byte[1];
						r_data_byte[2]<=r_data_byte[2];
						r_data_byte[3]<=r_data_byte[3];
						r_data_byte[4]<=r_data_byte[4];
						r_data_byte[5]<=r_data_byte[5];
						r_data_byte[6]<=r_data_byte[6];
						r_data_byte[7]<=r_data_byte[7];
						stop_bit<=3'd0;
						end
					endcase	
				end			
		
		//判断r_data_byte最高位，共有采样6次，如果采样结果有超过3次采样数据为1，则输出1.否则输出0.
		reg [7:0]data_byte;
		always@(posedge clk or negedge rst_n)
			if(!rst_n)
				data_byte<=8'd0;
			else if(bps_cnt==8'd159) begin
						data_byte[0]<=r_data_byte[0][2];
						data_byte[1]<=r_data_byte[1][2];
						data_byte[2]<=r_data_byte[2][2];
						data_byte[3]<=r_data_byte[3][2];
						data_byte[4]<=r_data_byte[4][2];
						data_byte[5]<=r_data_byte[5][2];
						data_byte[6]<=r_data_byte[6][2];
						data_byte[7]<=r_data_byte[7][2];
					end

endmodule 